The present invention relates to a process for the manufacture of semiconductor single crystals that are doped with a dopant, in particular to compound semiconductor single crystals having high electrical conductivity of n-type and p-type, preferably n-type. The process comprises solidifying a melt of the semiconductor material in a crucible by using a seed crystal of the same semiconductor material as the semiconductor single crystal to be produced.
In various fields of semiconductor technology, in particular for the manufacture of semiconductor lasers, luminescence diodes and solar cells, compound semiconductor crystals or substrate wafers are required that have electrical conductivity lying within a specific range determined by the respective use. This conductivity is achieved by doping with appropriate dopants. Furthermore, by choosing the dopant, it can be determined whether the charge transport within the semiconductor is dominated by electrons or defect electrons. The value of the electrical conductivity is determined by the concentration of the dopant in the semiconductor single crystal.
A common process for the manufacture of semiconductor single crystals, and specifically of compound semiconductor single crystals, includes the step of solidifying the semiconductor melt in a crucible, which is formed, e.g., of boron nitride. The semiconductor melt may be covered by a cover melt, which is, e.g., formed of boron oxide (B2O3), in order to avoid an evaporation of volatile components of the semiconductor melt. The crucible normally is a cylindrical container, which conically tapers toward its lower end in its operating orientation, and extends to a cylindrical portion having a lower diameter at the lower end which may be closed at its bottom side. The lower cylindrical portion serves for receiving a seed crystal. By means of heating elements provided outside the crucible, a three-dimensional, preferably radially symmetric, temperature field is applied, wherein the symmetry axis essentially corresponds to the symmetry axis of the crucible. The temperature field is formed such that, at each location within the crucible, a temperature gradient having a vertical component is present. During the crystal growth process, the temperature field is changed such that the solidification/temperature-isotherm shifts in a vertical direction, starting from the seed crystal. There is a good controllability of the crystal growth process, if the solidification front, i.e., the phase interface between the crystal and the semiconductor melt, differs only slightly from the solidification/temperature-isotherm over the whole cross section of the crucible and at each point in time, of the process.
In the conventional manufacturing processes for semiconductor single crystals, and specifically compound semiconductor single crystals, doping is carried out by adding the dopant, in elementary or chemically bound form, to the crucible before or after melting the semiconductor material, and subsequently carrying out the process of single crystal growth by solidification of the melted semiconductor material. In a specific work of Fornari et al. (Journal of Crystal Growth 63 (1983), 415-418) pertaining to Si-doped GaAs single crystal based on the LEC process, essentially the whole amount of the dopant silicon, which corresponded to the desired dopant concentration, was correspondingly pre-charged into the melt (2.5×1019 atoms/cm3), after which a small amount of silicon was further added to the melt during the subsequent crystal growth, for gradually reaching a maximum concentration of 3×1019 atoms/cm3 in the melt. Fomari et al. tried to solve the problem of generating solid particles in the melt, which may flow on top of the GaAs melt and thus, specifically in the LEC process where the crystal is pulled out of the melt, may disturb the single crystal growth by a contact of the particles with the phase interface between crystal and melt. This phenomenon however does not pose a problem in VGF-processes, because the phase interface between crystal and melt does not have a contact to the upper melt surface.
In conventional processes, the amount of the pre-charged dopant is determined such that a dopant concentration is adjusted in the melt. Considering the effective distribution coefficient, this leads to an incorporation of the dopant into the single crystal at the desired concentration. For achieving a high conductivity, a high amount of dopant is added into the melt.
When using a covering melt, e.g., with a boron oxide melt, the semiconductor melt is directly in contact with this melt during the whole period of the crystal growth process. Depending on the affinity of the chosen dopant in relation to oxygen, an oxidation of the dopant and a dissolution of the oxide in the boron oxide melt occurs partially. As a result, a part of the dopant is removed from the semiconductor melt. At the same time, the impurity generated by the reaction (in the example here: boron) is incorporated into the semiconductor melt. The prepared crystals may thus be contaminated by this impurity (e.g., boron) at a substantial concentration, thereby impairing the quality. For example, an impurity with boron may lead to formation of electrically compensating defects and thus to a decrease of the electrical conductivity.
In [1] JP 2000-109400A, [2] JP 2004-217508A and [3] JP 10-279398A, processes are described according to which a homogenization of silicon inclusion into a gallium arsenide single crystal is to be achieved. The axial homogeneity of the electrical conductivity of the single crystal is said to be improved thereby. The processes are based on stirring a boron oxide cover melt at a certain point of time, or at several points of time during the crystal growth process. In the processes described in [2] and [3], a SiO2-enriched boron oxide cover melt is used in order to suppress oxidation of the silicon dopant contained in the gallium arsenide melt. For the reaction equilibrium between silicon, boron oxide and SiO2, the concentration of boron oxide at the phase borderline to the gallium arsenide melt is significant. Stirring the boron oxide cover melt leads to its thorough mixing and thus to a decrease in the SiO2-concentration at the interface to the gallium arsenide melt. In this way, the oxidation of silicon contained in the gallium arsenide melt is enhanced, and the silicon concentration in a gallium arsenide single crystal increases less at its end than without this measure. However, by oxidizing silicon with boron oxide, the concentration of the boron impurity in the gallium arsenide melt and in the gallium arsenide single crystal is increased.
The processes described in [1], [2] and [3] enable a certain homogenization of silicon inclusion into a gallium arsenide single crystal, but the concentration of boron impurity in the gallium arsenide melt and in the gallium arsenide single crystal is increased. This disadvantageously affects the quality of the generated crystals. In the manufacture of a gallium arsenide single crystal according to a process described in JP 2004-115339A [4], the gallium arsenide melt is separated from the boron oxide cover melt by an isolating layer of liquid boron arsenide. The oxidation of the dopant silicon is diminished thereby.
US 2004/0187768 A1 follows another concept for the manufacture of doped GaAs crystals of p-type that have a very low dislocation density of <100 cm−2. The low dislocation density is obtained by mandatorily adding 4 types of dopants to the GaAs starting material, namely, Zn as a p-type dopant, Si as an n-type dopant, B as a. neutral atom, and In as a neutral atom. That is, a high p-type conductivity is obtained by doping with zinc, while the other dopants, Si, B and In, lead to an impurity hardening effect. The necessity of purposively doping 4 types of dopants limits the applicability of such wafer materials.
U.S. Pat. No. 3,496,118 describes a process for increasing electrical conductivity of III-V semiconductor compounds. A melt of the III-V semiconductor compound is produced in the presence of an impurity selected from Al, Sb, Bi, In and Pb, and a crystal is formed at a solidification point which is intentionally lowered by the added impurity. As conductivity generating impurities, doping atoms are added that are selected from Mn, Te, Se, S, Cd, Zn, Sn, Ge and Si. The amount of impurity being added is so high that a III-V-multiple component melt and thus a corresponding crystal (ternary, quaternary) is produced, rather than dealing with doping or formation of a binary III-V single crystal.
In order to satisfy the need for III-V semiconductor single crystals having a desirably high charge carrier mobility of the dopant, the conventional manufacture normally is carried out without a cover melt of, e.g., B2O3, in a boat for horizontal solidification of the semiconductor melt. However, this manufacturing principle is applicable only to the manufacture of III-V semiconductor crystals having small diameters, such as, normally 2 inches (1 inch=2.54 cm) or up to maximally 3 inches. For example, the abstract of KR 1019920010134 B1 describes a Bridgman process in which the solidification of the GaAs melt is carried out in a sealed quartz ampoule, without a boron oxide cover melt. A GaAs single crystal produced by this process has a electron mobility of 2,000 to 4,000 cm/Vs and an electron concentration of 1017-1018 cm−3.
To produce III-V semiconductor crystals having larger diameters, particularly diameters of at least 100 mm, the process of vertically directed solidification of a melt of the semiconductor material conventionally required use of a cover melt of, e.g., boron oxide. However, this leads to the problems described above.
The conventional processes are not successful for manufacturing semiconductor single crystals that have a high electrical conductivity, while at the same time providing a high process security, yield and quality.